The invention relates to duty cycle correction circuits. More particularly, the invention relates to counter-based duty cycle correction systems and methods.
Clock signals are used in virtually every integrated circuit (IC) and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit might change state. Frequently, both edges (rising and falling) of the clock signal are used. For example, in a Master-Slave flip-flop, data is read into the flip-flop on one edge of the clock signal, and then appears at the output terminal of the flip-flop on the other edge. Because the Master-Slave flip-flop is performing logic functions during each half of the clock cycle, the two states of the clock (high and low) are preferably each of approximately equal length. This condition is called a xe2x80x9c50 percent duty cyclexe2x80x9d.
If one state of the clock signal is appreciably longer than the other state, the clock signal is xe2x80x9casymmetricalxe2x80x9d (e.g., the clock signal is low longer than it is high). This limitation is not uncommon. For example, duty cycles of about 10 percent (i.e., 10 percent high, 90 percent low) are often seen. Under these conditions, the frequency at which a circuit can operate can be limited by the length of the shorter state (e.g., by the length of time that the clock signal is high). Therefore, the circuit operates at an unnecessarily low frequency. Applications that can be subject to this limitation include, for example, random access memory (RAM) read/write accesses and clock data recovery (CDR) and storage applications.
To overcome this limitation, circuit designers can extract a 50 percent duty cycle clock from an asymmetrical clock signal using a phase-lock loop (PLL) circuit. However, PLLs are analog in nature and take a very long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are difficult to design, and often are not feasible in a given circuit or system. Digital delay lock loops (DLLs) can also be used for duty cycle correction. However, DLLs are typically large circuits, and DLLs cannot be used in applications where the input clock frequency is unknown. Therefore, in some applications duty cycle correction is impractical or impossible using known circuits and methods.
Therefore, it is desirable to provide duty cycle correction circuits and methods that enable a circuit designer to correct an asymmetrical clock to about a 50 percent duty cycle, using a fairly simple circuit that consumes a relatively small amount of area when implemented in an integrated circuit (IC).
The invention provides duty cycle correction (DCC) circuits and methods that accept an asymmetrical input clock signal and provide therefrom an output clock signal having a 50 percent duty cycle. A DCC circuit according to the invention includes first and second counters, a register, a comparator, and an output clock generator. The first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in the register. Thus, the value stored in the register is one-half the number of counts in the input clock period, and represents a point halfway through the input clock period. The first counter is then reset, to be ready for the next count.
Each time the input clock signal changes from a first state to a second state (e.g., on each rising edge of the input clock signal), the output clock generator also changes the output clock signal from the first state to the second state. At the same time, the second counter is enabled. The comparator compares the value in the second counter to the value stored in the register. When the comparator signals that the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached. At this point, the output clock generator changes the output clock signal from the second state back to the first state. A reset signal is also issued to the second counter circuit. Thus, the second counter circuit is ready to begin counting again the next time the input clock signal changes from the first state to the second state.
The frequency with which the first counter is activated to count the period of the first clock signal can be selected, for example, based on the variation in the period of the input clock signal. In one embodiment, the first counter is enabled for one input clock period out of every four.